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DARPAが発注したワンチップスパコンは64gigaflopsを実現、さらにリコンフィギャラブルでメモリー内蔵 Monarch System-On-a-Chip Excels In Early Tes
http://www.medicalnewstoday.com/medicalnews.php?newsid=66028&nfid=rssfeeds
Monarch System-On-a-Chip Excels In Early Testing
28 Mar 2007
DARPAとの契約に基づいてUSC Information Sciences Institute と Raytheonが開発中のMONARCH(Morphable Networked Micro-Architecture)は宇宙空間レーダー、ビデオ処理用に設計され、いずれスマートカー、ハイウェイ、医療画像処理のような商用、更にGPSジャミング（妨害）排除を含む軍事目的に
この革命的なプロセッサパッケージは最近、行われた実験で当初の設計目標を超え、多様なコンピューティングタスクに対応してアーキテクチャー（内部構成）を変えることができる。MONARCHはとりあえず宇宙レーダーspace radarとビデオ処理に利用の予定。
Raytheon社は同時にハイエンドの商業アプリケーション開発に投資を続けており，スマートカー、高速道路、医療用画像処理、さらに軍事用にGPSのジャミング（妨害）排除といった分野へ適用を狙っている。
まず、フェイズI 及びIIでMONARCHアーキテクチャーを開発。
”要するにチップ上にスパコンを作ろうとしているのだが、単なるスパコンではなく、複数のタスクからなる個々の部分に自動的に最適化するリコンフィギャラブル（再構成可能）なスパコンである”とGranacki, director of the Advanced Systems Division at ISIでResearch Associate Professor of Electrical Engineering Systems and Biomedical Engineering in the USC Viterbi School of Engineeringは言う。
その柔軟性によって、MONARCHはコンピュータシステムに必要なハードウエアの量を大幅に削減し，同時に，極端に高いスループット（teraflop)を実現する。それは、たった一個のMONARCH機器にメモリを統合していることによる。
より大きなシステム（implementation）に対しては、MONARCHのもつ、機器を"morph"（変身、変形）させる機能により、更に小型化が可能となり、じっと座って入力を待つスパコンではなく、downstream task(下流、より現場に近い作業) に適用可能となる。
MONARCHチップは同時に、これをいくつも組み合わせて(based on arrays of devices)、いろいろな規模のシステムのシステム部品としても使うことができる。これは２個の外部メモリーインターフェースを持っており、大規模な作業処理に対応する。最終的に、業界標準機器接続のために各チップは２個のRapidIOインターフェースを持つことになる。
MONARCHのpolymorphic（複数モーフィング？）機能と超高性能（super efficiency)により、超小型、低消費電力、さらに、一部（宇宙空間での使用のシステムについて特に）放射線被爆耐性を必要とする国防省のシステム開発を可能にするとGranackiは言う。
一般的には、チップはフロントでの信号処理とバックエンドでの制御、データ処理に最適化して設計されている。
MONARCHのマイクロアーキテクチャーはそれ自身で処理を簡単に、自動的にリコンフィギャーする点でユニーックである。MONARCHは前例のない計算処理能力と高度に柔軟性の高い帯域に加えて、現時点で可能な水準を遥かに凌駕する最高のエネルギー消費効率を実現し、同時に、完全にプログラム可能である。
Phase IIIの予備試験で、この新しいデバイスのプロトタイプのシステムはわずか、一個で、64 gigaflops (floating point operations per second) を60 gigabytes per second of memory bandwidth以上、更に43 gigabytes per second of off-chip data bandwidthを実現。
特定目的にそのアーキテクチャを適合させる能力に加え、MONARCHコンピュータは同時に、現在入手可能なもので最高水準の低消費電力を実現。MONARCHはIntel quad-core Xeon chipと比較して10倍のエネルギー効率を実現したとRaytheonの担当者は述べた。
A revolutionary processor package that changes its architecture to adapt to the demands of different computing tasks more than met design expectations in recent trials.
Near-term applications for the MONARCH (Morphable Networked Micro-Architecture) system designed by the USC Information Sciences Institute and Raytheon include space radar and video processing, which require small size and low power.
Raytheon also is investigating high-end commercial applications such as use in smart cars and highways and in medical imaging, as well as exploring a method for countering GPS jamming for the military.
During Phases I and II of the program, an ISI group headed by John Granacki developed the MONARCH architecture, working with the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems on a contract from DARPA.
Granacki is director of the Advanced Systems Division at ISI, and Research Associate Professor of Electrical Engineering Systems and Biomedical Engineering in the USC Viterbi School of Engineering.
"What we have been creating is essentially a supercomputer on a chip," he said, "and not just a supercomputer, but a flexible supercomputer reconfigures itself into the optimal supercomputer for each specific part of a multi-part task."
This flexibility means MONARCH allows a significant reduction of the amount of hardware (and therefore power) required for computing systems, while still achieving extremely high (teraflop) throughput. Because of the memory integrated on the chip, very small systems may be implemented with only a single MONARCH device.
For larger implementations, hardware demand is further reduced by MONARCH's ability to "morph" devices to so they can perform downstream tasks instead of sitting idle while waiting for fresh input
The MONARCH chip may also serve as a system building block, allowing systems of different sizes to be based on arrays of devices. Each device has input/output ports to enable seamless data movement among multiple chips. The device has two off-chip memory interfaces for large problems. Finally, every chip is equipped with two RapidIO interfaces for connecting to industry-standard equipment.
According to Granacki, MONARCH's polymorphic capability and super efficiency enable the development of DoD systems that need very small size, low power, and in some cases (particularly systems to be used in space) radiation tolerance.
"Typically, a chip is optimally designed either for front-end signal processing or back-end control and data processing," explained Nick Uros, vice president for the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems.
"The MONARCH micro-architecture is unique in its ability to reconfigure itself to optimize processing on the fly. MONARCH provides exceptional compute capacity and highly flexible data bandwidth capability with beyond state-of-the- art power efficiency, and it's fully programmable."
In preliminary tests in the Phase III evaluation, a prototype system consisting of just one of the new devices, provided sustained throughput of 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.
In addition to the ability to adapt its architecture for a particular objective, the MONARCH computer is also believed to be the most power- efficient processor available. "MONARCH outperformed the Intel quad-core Xeon chip by a factor of 10," said Michael Vahey, Raytheon's principal investigator for the company's MONARCH technology.
###
Granacki's ISI MONARCH team includes ISI Project Leaders Jeff LaCoss and Jeff Draper.
Besides USC, subcontracting team members included Craig Steele of Exogi, Inc., Sudhakar Yalamanchili of Georgia Tech, and James Kulp of Mercury Computer Corporation Georgia Institute of Technology, Mercury Computer Systems and IBM's Global Engineering Solutions division.
Contact: Eric Mankin
University of Southern California
Monarch System-On-a-Chip Excels In Early Testing
28 Mar 2007
DARPAとの契約に基づいてUSC Information Sciences Institute と Raytheonが開発中のMONARCH(Morphable Networked Micro-Architecture)は宇宙空間レーダー、ビデオ処理用に設計され、いずれスマートカー、ハイウェイ、医療画像処理のような商用、更にGPSジャミング（妨害）排除を含む軍事目的に
この革命的なプロセッサパッケージは最近、行われた実験で当初の設計目標を超え、多様なコンピューティングタスクに対応してアーキテクチャー（内部構成）を変えることができる。MONARCHはとりあえず宇宙レーダーspace radarとビデオ処理に利用の予定。
Raytheon社は同時にハイエンドの商業アプリケーション開発に投資を続けており，スマートカー、高速道路、医療用画像処理、さらに軍事用にGPSのジャミング（妨害）排除といった分野へ適用を狙っている。
まず、フェイズI 及びIIでMONARCHアーキテクチャーを開発。
”要するにチップ上にスパコンを作ろうとしているのだが、単なるスパコンではなく、複数のタスクからなる個々の部分に自動的に最適化するリコンフィギャラブル（再構成可能）なスパコンである”とGranacki, director of the Advanced Systems Division at ISIでResearch Associate Professor of Electrical Engineering Systems and Biomedical Engineering in the USC Viterbi School of Engineeringは言う。
その柔軟性によって、MONARCHはコンピュータシステムに必要なハードウエアの量を大幅に削減し，同時に，極端に高いスループット（teraflop)を実現する。それは、たった一個のMONARCH機器にメモリを統合していることによる。
より大きなシステム（implementation）に対しては、MONARCHのもつ、機器を"morph"（変身、変形）させる機能により、更に小型化が可能となり、じっと座って入力を待つスパコンではなく、downstream task(下流、より現場に近い作業) に適用可能となる。
MONARCHチップは同時に、これをいくつも組み合わせて(based on arrays of devices)、いろいろな規模のシステムのシステム部品としても使うことができる。これは２個の外部メモリーインターフェースを持っており、大規模な作業処理に対応する。最終的に、業界標準機器接続のために各チップは２個のRapidIOインターフェースを持つことになる。
MONARCHのpolymorphic（複数モーフィング？）機能と超高性能（super efficiency)により、超小型、低消費電力、さらに、一部（宇宙空間での使用のシステムについて特に）放射線被爆耐性を必要とする国防省のシステム開発を可能にするとGranackiは言う。
一般的には、チップはフロントでの信号処理とバックエンドでの制御、データ処理に最適化して設計されている。
MONARCHのマイクロアーキテクチャーはそれ自身で処理を簡単に、自動的にリコンフィギャーする点でユニーックである。MONARCHは前例のない計算処理能力と高度に柔軟性の高い帯域に加えて、現時点で可能な水準を遥かに凌駕する最高のエネルギー消費効率を実現し、同時に、完全にプログラム可能である。
Phase IIIの予備試験で、この新しいデバイスのプロトタイプのシステムはわずか、一個で、64 gigaflops (floating point operations per second) を60 gigabytes per second of memory bandwidth以上、更に43 gigabytes per second of off-chip data bandwidthを実現。
特定目的にそのアーキテクチャを適合させる能力に加え、MONARCHコンピュータは同時に、現在入手可能なもので最高水準の低消費電力を実現。MONARCHはIntel quad-core Xeon chipと比較して10倍のエネルギー効率を実現したとRaytheonの担当者は述べた。
A revolutionary processor package that changes its architecture to adapt to the demands of different computing tasks more than met design expectations in recent trials.
Near-term applications for the MONARCH (Morphable Networked Micro-Architecture) system designed by the USC Information Sciences Institute and Raytheon include space radar and video processing, which require small size and low power.
Raytheon also is investigating high-end commercial applications such as use in smart cars and highways and in medical imaging, as well as exploring a method for countering GPS jamming for the military.
During Phases I and II of the program, an ISI group headed by John Granacki developed the MONARCH architecture, working with the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems on a contract from DARPA.
Granacki is director of the Advanced Systems Division at ISI, and Research Associate Professor of Electrical Engineering Systems and Biomedical Engineering in the USC Viterbi School of Engineering.
"What we have been creating is essentially a supercomputer on a chip," he said, "and not just a supercomputer, but a flexible supercomputer reconfigures itself into the optimal supercomputer for each specific part of a multi-part task."
This flexibility means MONARCH allows a significant reduction of the amount of hardware (and therefore power) required for computing systems, while still achieving extremely high (teraflop) throughput. Because of the memory integrated on the chip, very small systems may be implemented with only a single MONARCH device.
For larger implementations, hardware demand is further reduced by MONARCH's ability to "morph" devices to so they can perform downstream tasks instead of sitting idle while waiting for fresh input
The MONARCH chip may also serve as a system building block, allowing systems of different sizes to be based on arrays of devices. Each device has input/output ports to enable seamless data movement among multiple chips. The device has two off-chip memory interfaces for large problems. Finally, every chip is equipped with two RapidIO interfaces for connecting to industry-standard equipment.
According to Granacki, MONARCH's polymorphic capability and super efficiency enable the development of DoD systems that need very small size, low power, and in some cases (particularly systems to be used in space) radiation tolerance.
"Typically, a chip is optimally designed either for front-end signal processing or back-end control and data processing," explained Nick Uros, vice president for the Advanced Concepts and Technology group of Raytheon Space and Airborne Systems.
"The MONARCH micro-architecture is unique in its ability to reconfigure itself to optimize processing on the fly. MONARCH provides exceptional compute capacity and highly flexible data bandwidth capability with beyond state-of-the- art power efficiency, and it's fully programmable."
In preliminary tests in the Phase III evaluation, a prototype system consisting of just one of the new devices, provided sustained throughput of 64 gigaflops (floating point operations per second) with more than 60 gigabytes per second of memory bandwidth and more than 43 gigabytes per second of off-chip data bandwidth.
In addition to the ability to adapt its architecture for a particular objective, the MONARCH computer is also believed to be the most power- efficient processor available. "MONARCH outperformed the Intel quad-core Xeon chip by a factor of 10," said Michael Vahey, Raytheon's principal investigator for the company's MONARCH technology.
###
Granacki's ISI MONARCH team includes ISI Project Leaders Jeff LaCoss and Jeff Draper.
Besides USC, subcontracting team members included Craig Steele of Exogi, Inc., Sudhakar Yalamanchili of Georgia Tech, and James Kulp of Mercury Computer Corporation Georgia Institute of Technology, Mercury Computer Systems and IBM's Global Engineering Solutions division.
Contact: Eric Mankin
University of Southern California
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